Thin film fuse phase change cell with thermal isolation layer and manufacturing method

ABSTRACT

A memory device comprising a first electrode having a top side, a second electrode having a top side and an insulating member between the first electrode and the second electrode. The insulating member has a thickness between the first and second electrodes near the top side of the first electrode and the top side of the second electrode. A bridge of memory material crosses the insulating member, and defines an inter-electrode path between the first and second electrodes across the insulating member. An array of such memory cells is provided. The bridge comprises an active layer of memory material on the first side having at least two solid phases and a blanket of thermal insulating material overlying the memory material having thermal conductivity less than that of an overlying electrically insulating layer.

RELATED APPLICATION DATA

The present application is a continuation-in-part of U.S. patent application Ser. No. 11/155,067; filed 17 Jun. 2005, which is incorporated by reference as if fully set forth herein.

PARTIES TO A JOINT RESEARCH AGREEMENT

International Business Machines Corporation, a New York corporation; Macronix International Corporation, Ltd., a Taiwan corporation, and Infineon Technologies A.G., a German corporation, are parties to a Joint Research Agreement.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to high density memory devices based on phase change based memory materials, including chalcogenide based materials and other materials, and to methods for manufacturing such devices.

2. Description of Related Art

Phase change based memory materials are widely used in read-write optical disks. These materials have at least two solid phases, including for example a generally amorphous solid phase and a generally crystalline solid phase. Laser pulses are used in read-write optical disks to switch between phases and to read the optical properties of the material after the phase change.

Phase change based memory materials, like chalcogenide based materials and similar materials, also can be caused to change phase by application of electrical current at levels suitable for implementation in integrated circuits. The generally amorphous state is characterized by higher resistivity than the generally crystalline state, which can be readily sensed to indicate data. These properties have generated interest in using programmable resistive material to form nonvolatile memory circuits, which can be read and written with random access.

The change from the amorphous to the crystalline state is generally a lower current operation. The change from crystalline to amorphous, referred to as reset herein, is generally a higher current operation, which includes a short high current density pulse to melt or breakdown the crystalline structure, after which the phase change material cools quickly, quenching the phase change process, allowing at least a portion of the phase change structure to stabilize in the amorphous state. It is desirable to minimize the magnitude of the reset current used to cause transition of phase change material from crystalline state to amorphous state. The magnitude of the reset current needed for reset can be reduced by reducing the size of the phase change material element in the cell and of the contact area between electrodes and the phase change material, so that higher current densities are achieved with small absolute current values through the phase change material element.

One direction of development has been toward forming small pores in an integrated circuit structure, and using small quantities of programmable resistive material to fill the small pores. Patents illustrating development toward small pores include: Ovshinsky, “Multibit Single Cell Memory Element Having Tapered Contact,” U.S. Pat. No. 5,687,112, issued Nov. 11, 1997; Zahorik et al., “Method of Making Chalogenide [sic] Memory Device,” U.S. Pat. No. 5,789,277, issued Aug. 4, 1998; Doan et al., “Controllable Ovonic Phase-Change Semiconductor Memory Device and Methods of Fabricating the Same,” U.S. Pat. No. 6,150,253, issued Nov. 21, 2000.

Problems have arisen in manufacturing such devices with very small dimensions, and with variations in process that meet tight specifications needed for large-scale memory devices. One problem associated with the small dimensions of phase change cells has arisen because of the thermal conductivity of materials surrounding the active region. In order to cause phase transitions, the temperature of the active region in the phase change material must reach phase transition thresholds. However, heat generated by the current through the material is conducted away by surrounding structures. This conduction of heat away from the active region in the phase change material slows down the heating effect of the current and interferes with the operation to change the phase.

It is desirable therefore to provide a memory cell structure having small dimensions and low reset currents, and a method for manufacturing such structure that meets tight process variation specifications needed for large-scale memory devices. It is further desirable to provide a manufacturing process and a structure, which are compatible with manufacturing of peripheral circuits on the same integrated circuit.

SUMMARY OF THE INVENTION

A phase change random access memory PCRAM device is described suitable for use in large-scale integrated circuits. Technology described herein includes a memory device comprising a first electrode having a top side, a second electrode having a top side and an insulating member between the first electrode and the second electrode. The insulating member has a thickness between the first and second electrodes near the top side of the first electrode and the top side of the second electrode. A thin film bridge crosses the insulating member, and defines an inter-electrode path between the first and second electrodes across the insulating member. The thin film bridge includes an active layer of phase change material, and a blanket of material providing thermal isolation of the active layer from the overlying structure. The material in the blanket providing thermal insulation can comprise the same phase change material used for the active region. The blanket of material providing thermal isolation can comprise a composite structure including a first isolation layer, and a second thermally insulating layer, where the isolation layer electrically isolates the active layer from the thermally insulating material, and/or acts as a diffusion layer blocking material migration between the active layer and the thermally insulating material. The inter-electrode path across the insulating member has a path length defined by the width of the insulating member. For the purpose of illustration, the bridge can be thought of as having a structure like a fuse. For the phase change memory however, and unlike a fuse, the bridge comprises memory material having at least two solid phases that are reversible, such as a chalcogenide-based material or other related material, by applying a current through the material or applying a voltage across the first and second electrodes. A layer of electrically insulating material overlies the blanket of thermally insulating material, wherein the thermally insulating material in the blanket has a thermal conductivity less than that of the electrically insulating material

The volume of memory material subject of phase change can be very small, determined by the thickness of the insulating member (path length in the x-direction), the thickness of the thin film used to form the bridge (y-direction), and the width of the bridge orthogonal to the path length (z-direction). The thickness of the insulating member and the thickness of the thin film of memory material used to form the bridge are determined in embodiments of the technology by thin film thicknesses which are not limited by the two graphic processes used in manufacturing the memory cell. The width of the bridge is also smaller than a minimum feature size F that is specified for a lithographic process used in patterning the layer of material in embodiments of the present invention. In one embodiment, the width of the bridge is defined using photoresist trimming technologies in which a mask pattern is used to define a lithographical photoresist structure on the chip having the minimum feature size F, and the photoresist structure is trimmed by isotropic etching to achieve a feature size less than F. The trimmed photoresist structure is then used to lithographically transfer the more narrow pattern onto the layer of memory material. Also, other techniques can be used to form narrow lines of material in a layer on an integrated circuit. Accordingly, a phase change memory cell with simple structure achieves very small reset current and low power consumption, and is easily manufactured.

In embodiments of the technology described herein, an array of memory cells is provided. In the array, a plurality of electrode members and insulating members therebetween comprise an electrode layer on an integrated circuit. The electrode layer has a top surface which is substantially planar in some embodiments of the invention. The corresponding plurality of thin film bridges, with thermally insulating blankets, across the insulating members between pairs of electrode members comprise memory elements on the top surface of the electrode layer. A current path from a first electrode in the electrode layer through a thin film bridge on the top surface of the electrode layer to a second electrode in the electrode layer is established for each memory cell in the array.

Circuitry below the electrode layer on integrated circuits described herein can be implemented using well understood technology for logic circuitry and memory array circuitry, such as CMOS technology.

Also, in one array embodiment described herein, circuitry above the electrode layer and the array of bridges with thermally insulating blankets includes a plurality of bit lines. In an embodiment having bit lines above the electrode layer that is described herein, electrode members in the electrode layer which act as a first electrode for a memory cell are shared so that a single electrode member provides a first electrode for two memory cells in a column of the array. Also, in an embodiment that is described herein, bit lines in the plurality of bit lines are arranged along corresponding columns in the array, and two adjacent memory cells in the corresponding columns share a contact structure for contacting said first electrodes.

A method for manufacturing a memory device is also described. The method comprises forming an electrode layer on a substrate which comprises circuitry made using front-end-of-line procedures. The electrode layer in this method has a top surface. The electrode layer includes a first electrode and a second electrode, and an insulating member between the first and second electrodes for each phase change memory cell to be formed. The first and second electrodes and the insulating member extend to the top surface of the electrode layer, and the insulating member has a width between the first and second electrodes at the top surface, as described above in connection with the phase change memory cell structures. The method also includes forming a bridge of memory material with thermally insulating blankets on the top surface of the electrode layer across the insulating member for each memory cell to be formed. The bridge comprises a film of memory material having a first side and a second side and contacts the first and second electrodes on the first side. The bridge defines an inter-electrode path between the first and second electrodes across the insulating member having a path length defined by the width of the insulating member. In embodiments of the method, an access structure over the electrode layer is made by forming a patterned conductive layer over said bridge, and forming a contact between said first electrode and said patterned conductive layer.

Other aspects and advantages of the present invention can be seen from review of the figures, the detailed description and the claims which follow.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates an embodiment of a thin film bridge phase change memory element.

FIG. 2 illustrates a structure for a pair of phase change memory elements with access circuitry below an electrode layer and bit lines above the electrode layer.

FIG. 3 shows a layout or plan view for the structure illustrated in FIG. 2.

FIG. 4 is a schematic diagram for a memory array comprising phase change memory elements.

FIG. 5 is a block diagram of an integrated circuit device including a thin film fuse phase change memory array and other circuitry.

FIG. 6 illustrates a first step in a dual damascene procedure used to form the electrode layer for a memory device as described herein.

FIG. 7 illustrates a second step in a dual damascene procedure used to form the electrode layer for a memory device as described herein.

FIG. 8 illustrates a third step in a dual damascene procedure used to form the electrode layer for a memory device as described herein.

FIG. 9 illustrates a fourth step in a dual damascene procedure used to form the electrode layer for a memory device as described herein.

FIG. 10 illustrates a fifth step in a dual damascene procedure used to form the electrode layer for a memory device as described herein.

FIG. 11 illustrates a sixth step in a dual damascene procedure used to form the electrode layer for a memory device as described herein.

FIG. 12 illustrates a seventh step in a dual damascene procedure used to form the electrode layer for a memory device as described herein.

FIG. 13 illustrates an eighth step in a dual damascene procedure used to form the electrode layer for a memory device as described herein.

FIG. 14 illustrates a ninth step in a dual damascene procedure used to form the electrode layer for a memory device as described herein.

FIG. 15 illustrates a tenth step in a dual damascene procedure used to form the electrode layer for a memory device as described herein.

FIG. 16 illustrates an eleventh step in a dual damascene procedure used to form the electrode layer for a memory device as described herein.

DETAILED DESCRIPTION

A detailed description of thin film fuse phase change memory cells, arrays of such memory cells, and methods for manufacturing such memory cells, is provided with reference to FIGS. 1-16.

FIG. 1 illustrates a basic structure of a memory cell 10 including a bridge 11 of memory material on an electrode layer which comprises a first electrode 12, a second electrode 13, and an insulating member 14 between the first electrode 12 and the second electrode 13. As illustrated, the first and second electrodes 12, 13 have top surfaces 12 a and 13 a. Likewise the insulating member 14 has a top surface 14 a. The top surfaces 12 a, 13 a, 14 a of the structures in the electrode layer define a substantially planar top surface for the electrode layer in the illustrated embodiment. In other embodiments, top surfaces 12 a, 14 a and 13 a are not co-planar, with the insulating member 14 extending up forming an insulating wall between the electrodes, for example. The bridge 11 of memory material includes an active layer 15 of memory material on the top surface of the electrode layer, so that contacts between the first electrode and the bridge 11 and between the second electrode 13 and the bridge 11 are made on the bottom side of the active layer 15. The bridge 11 includes a thermally insulating blanket including barrier layer 16 and layer 17 of thermally insulating material covering the active layer 15 of memory material, contributing to the confinement heat generated in the active layer 15 within an active region of the memory cell. The barrier layer 16 comprises a material, such as silicon nitride or silicon oxide, which provides electrical isolation between active layer 15 and layer 17. The barrier layer 16 also acts as a diffusion barrier between the thermally insulating material in layer 17 and the memory material in active layer 15. In the embodiment shown, the blanket covers the top of active layer 15 only. In other embodiments, the blanket extends over the sides of the active layer 15 as well. Also, the barrier layer 16 and the thermally insulating layer 17 may comprise respective multilayer composites.

Access circuitry can be implemented to contact the first electrode 12 and the second electrode 13 in a variety of configurations for controlling the operation of the memory cell, so that it can be programmed to set the active layer 15 of bridge 11 in one of the two solid phases that can be reversibly implemented using the memory material. For example, using a chalcogenide-based phase change memory material, the memory cell may be set to a relatively high resistivity state in which at least a portion of the bridge in the current path is in an amorphous state, and a relatively low resistivity state in which most of the bridge in the current path is in a crystalline state.

The active region in the active layer 15 is the region in which the material is induced to change between the at least two solid phases. In the embodiment shown, the active region lies within the active layer 15 roughly over the insulating member 14. As can be appreciated, the active region can be made extremely small in the illustrated structure, reducing the magnitude of current needed to induce the phase changes.

The length L (x-dimension) of the active region is defined by the thickness of the insulating member 14 at its top surface 14 a, between the first electrode 12 and the second electrode 13. This length L can be controlled by controlling the width of the insulating member 14 in embodiments of the memory cell. In representative embodiments, the width of the insulating member 14 can be established using a thin film deposition technique to form a thin sidewall dielectric on the side of an electrode stack. Thus, embodiments of the memory cell have a channel length L less than 100 nm. Other embodiments have a channel length L of about 40 nm or less. In yet other embodiments, the channel length is less than 20 nm. It will be understood that the channel length L can be even smaller than 20 nm, using thin film deposition techniques such as atomic layer deposition and the like, according to the needs of the particular application.

Likewise, the thickness T (y-dimension) of the active region can be very small in embodiments of the memory cell. This thickness T can be established using a thin film deposition technique on the top surfaces of the first electrode 12, insulating member 14, and second electrode 13. Thus, embodiments of the memory cell have a thickness T about 50 nm or less. Other embodiments of the memory cell have a thickness T of about 20 nm or less. In yet other embodiments, the thickness T is about 10 nm or less. It will be understood that the thickness T of the active region can be even smaller than 10 nm, using thin film deposition techniques such as atomic layer deposition and the like, according to the needs of the particular application, so long as the thickness is sufficient for the bridge to perform its purpose as memory element, having at least two solid phases, reversible by a current or by a voltage applied across the first and second electrodes.

The bridge width W (z-dimension) also defining the width of the active region, is likewise very small. This bridge width W is implemented in preferred embodiments, so that it has a width less than 100 nm. In some embodiments, the bridge width W is about 40 nm or less.

Embodiments of the memory cell include phase change based memory materials, including chalcogenide based materials and other materials, for the bridge 11. Chalcogens include any of the four elements oxygen (O), sulfur (S), selenium (Se), and tellurium (Te), forming part of group VI of the periodic table. Chalcogenides comprise compounds of a chalcogen with a more electropositive element or radical. Chalcogenide alloys comprise combinations of chalcogenides with other materials such as transition metals. A chalcogenide alloy usually contains one or more elements from column six of the periodic table of elements, such as germanium (Ge) and tin (Sn). Often, chalcogenide alloys include combinations including one or more of antimony (Sb), gallium (Ga), indium (In), and silver (Ag). Many phase change based memory materials have been described in technical literature, including alloys of: Ga/Sb, In/Sb, In/Se, Sb/Te, Ge/Te, Ge/Sb/Te, In/Sb/Te, Ga/Se/Te, Sn/Sb/Te, In/Sb/Ge, Ag/In/Sb/Te, Ge/Sn/Sb/Te, Ge/Sb/Se/Te and Te/Ge/Sb/S. In the family of Ge/Sb/Te alloys, a wide range of alloy compositions may be workable. The compositions can be characterized as Te_(a)Ge_(b)Sb_(100−(a+b)).

One researcher has described the most useful alloys as having an average concentration of Te in the deposited materials well below 70%, typically below about 60% and ranged in general from as low as about 23% up to about 58% Te and most preferably about 48% to 58% Te. Concentrations of Ge were above about 5% and ranged from a low of about 8% to about 30% average in the material, remaining generally below 50%. Most preferably, concentrations of Ge ranged from about 8% to about 40%. The remainder of the principal constituent elements in this composition was Sb. These percentages are atomic percentages that total 100% of the atoms of the constituent elements. (Ovshinsky '112 patent, cols 10-11.) Particular alloys evaluated by another researcher include Ge₂Sb₂Te₅, GeSb₂Te₄ and GeSb₄Te₇. (Noboru Yamada, “Potential of Ge—Sb—Te Phase-Change Optical Disks for High-Data-Rate Recording”, SPIE v. 3109, pp. 28-37 (1997).) More generally, a transition metal such as chromium (Cr), iron (Fe), nickel (Ni), niobium (Nb), palladium (Pd), platinum (Pt) and mixtures or alloys thereof may be combined with Ge/Sb/Te to form a phase change alloy that has programmable resistive properties. Specific examples of memory materials that may be useful are given in Ovshinsky '112 at columns 11-13, which examples are hereby incorporated by reference.

Phase change alloys are capable of being switched between a first structural state in which the material is in a generally amorphous solid phase, and a second structural state in which the material is in a generally crystalline solid phase in its local order in the active channel region of the cell. These alloys are at least bistable. The term amorphous is used to refer to a relatively less ordered structure, more disordered than a single crystal, which has the detectable characteristics such as higher electrical resistivity than the crystalline phase. The term crystalline is used to refer to a relatively more ordered structure, more ordered than in an amorphous structure, which has detectable characteristics such as lower electrical resistivity than the amorphous phase. Typically, phase change materials may be electrically switched between different detectable states of local order across the spectrum between completely amorphous and completely crystalline states. Other material characteristics affected by the change between amorphous and crystalline phases include atomic order, free electron density and activation energy. The material may be switched either into different solid phases or into mixtures of two or more solid phases, providing a gray scale between completely amorphous and completely crystalline states. The electrical properties in the material may vary accordingly.

Phase change alloys can be changed from one phase state to another by application of electrical pulses. It has been observed that a shorter, higher amplitude pulse tends to change the phase change material to a generally amorphous state. A longer, lower amplitude pulse tends to change the phase change material to a generally crystalline state. The energy in a shorter, higher amplitude pulse is high enough to allow for bonds of the crystalline structure to be broken and short enough to prevent the atoms from realigning into a crystalline state. Appropriate profiles for pulses can be determined, without undue experimentation, specifically adapted to a particular phase change alloy. In following sections of the disclosure, the phase change material is referred to as GST, and it will be understood that other types of phase change materials can be used. A material useful for implementation of a PCRAM described herein is Ce₂Sb₂Te₅.

Other programmable resistive memory materials may be used in other embodiments of the invention, including N₂ doped OST, Ge_(x)Sb_(y), or other material that uses different crystal phase changes to determine resistance; Pr_(x)Ca_(y)MnO₃, PrSrMnO, ZrOx, or other material that uses an electrical pulse to change the resistance state; TCNQ, PCBM, TCNQ-PCBM, Cu-TCNQ, Ag-TCNQ, C60-TCNQ, TCNQ doped with other metal, or any other polymer material that has bistable or multi-stable resistance state controlled by an electrical pulse.

The layer 17 of thermally insulating material may be the same material as used as the memory material, such as GST in an embodiment of the cell. In other embodiments, the layer 17 of thermally insulating material comprises polyimide or some other material that has a lower thermal conductivity than a dielectric layer overlying the bridge. Representative thermally insulating materials include materials that are a combination of the elements silicon Si, carbon C, oxygen O, fluorine F, and hydrogen H. Examples of thermally insulating materials which are candidates for use for the thermally insulating cap layer include SiO_, SiCOH, polyimide, polyamide, and fluorocarbon polymers. Other examples of materials which are candidates for use for the thermally insulating cap layer include fluorinated SiO₂, silsesquioxane, polyarylene ethers, parylene, fluoro-polymers, fluorinated amorphous carbon, diamond like carbon, porous silica, mesoporous silica, porous silsesquioxane, porous polyimide, and porous polyarylene ethers. A single layer or combination of layers can provide thermal and electrical insulation.

FIG. 2 depicts a structure for PCRAM cells. The cells are formed on a semiconductor substrate 21. Isolation structures such as shallow trench isolation STI dielectrics (not shown) isolate pairs of rows of memory cell access transistors. The access transistors are formed by n-type terminal 26 acting as a common source region and n-type terminals 25 and 27 acting as drain regions in a p-type substrate 21. Polysilicon word lines 23 and 24 form the gates of the access transistors. A dielectric fill layer (not illustrated) is formed over the polysilicon word lines. The layer is patterned and conductive structures, including common source line 28 and plug structures 29 and 30 are formed. The conductive material can be tungsten or other materials and combinations suitable for the plug and lines structures. The common source line 28 contacts the source region 26, and acts as a common source line along a row in the array. The plug structures 29 and 30 contact the drain terminals 25 and 27, respectively. The fill layer (not shown), the common source line 28 and the plug structures 29 and 30, have a generally planar top surface, suitable for formation of an electrode layer 31.

The electrode layer 31 includes electrode members 32, 33 and 34, which are separated from one another by an insulating member including fences 35 a and 35 b and base member 39, formed for example by a dual damascene process as described below. The base member 39 can be thicker than the fences 35 a, 35 b in embodiments of the structure, and separates the electrode member 33 from the common source line 28. For example the base member can be for instance, 80 to 140 nm thick while the fences are much narrower, as needed to reduce capacitive coupling between the source line 28 and the electrode member 33. The fences 35 a, 35 b comprise a thin film dielectric material on the sidewalls of electrode members 32, 34 in the illustrated embodiment, with a thickness at the surface of the electrode layer 31 determined by the damascene pattern thickness on the sidewalls.

A composite bridge including a layer 36 a of memory material, such as GST, with a blanket including a barrier layer 36 b and a thermally insulating layer 36 c, overlies the electrode layer 31 on one side traversing across the fence member 35 a, forming a first memory cell, and a thin film bridge including a layer 37 a of memory material, such as GST, with a blanket including a barrier layer 37 b and a thermally insulating layer 37 c, overlies the electrode layer 31 on another side traversing across the fence member 35 b, forming a second memory cell.

A dielectric fill layer (not illustrated) overlies the thin film bridges. The dielectric fill layer comprises silicon dioxide, a polyimide, silicon nitride or other dielectric fill materials. The thermally insulating layer 37 c of the blanket has a thermal conductivity that is less than that of the dielectric fill layer. Tungsten plug 38 contacts the electrode member 33. A patterned conductive layer 40, comprising metal or other conductive material, including bit lines in an array structure, overlies the dielectric fill layer, and contacts the plug 38 to establish access to the memory cells corresponding to the active layer 36 a of the bridge on the left and the active layer 37 a of the bridge on the right.

FIG. 3 shows the structure above the semiconductor substrate layer 21 of FIG. 2 in layout view. Thus, the word lines 23 and 24 are laid out substantially parallel to the common source line 28, along those in an array of memory cells. Plugs 29 and 30 contact terminals of access transistors in the semiconductor substrate and the underside of electrode members 32 and 34 respectively. Composite thin film bridges 36 and 37 of memory material and thermally insulating blankets overlie the electrode members 32, 33 and 34, and the insulating fences 35 a, 35 b separating the electrode members. Plug 38 contacts the electrode member 33 between the bridges 36 and 37 and the underside of a metal bit line 41 (transparent in FIG. 6) in the patterned conductive layer 40. Metal bit line 42 (not transparent) is also illustrated in FIG. 3 to emphasize the array layout of the structure.

In operation, access to the memory cell corresponding with bridge 36 is accomplished by applying a control signal to the word line 23, which couples the common source line 28 via terminal 25, plug 29, and electrode member 32 to the active layer 36 a of the bridge 36. Electrode member 33 is coupled via the contact plug 38 to a bit line in the patterned conductive layer 40. Likewise, access to the memory cell corresponding with bridge 37 is accomplished by applying a control signal to the word line 24.

It will be understood that a wide variety of materials can be utilized in implementation of the structure illustrated in FIGS. 5 and 6. For example, copper metallization can be used. Other types of metallization, including aluminum, titanium nitride, and tungsten based materials can be utilized as well. Also, non-metal conductive material such as doped polysilicon can be used. The electrode material in the illustrated embodiment is preferably TiN or TaN. Alternatively, the electrodes may be TiAlN or TaAlN, or may comprise, for further examples, one or more elements selected from the group consisting of Ti, W, Mo, Al, Ta, Cu, Pt, Ir, La, Ni, and Ru and alloys thereof. The inter-electrode fence members 35 a, 35 b may be silicon oxide, silicon oxynitride, silicon nitride, Al₂O₃, or other low K dielectrics. Alternatively, the inter-electrode insulating layer may comprise one or more elements selected from the group consisting of Si, Ti, Al, Ta, N, O, and C.

FIG. 4 is a schematic illustration of a memory array, which can be implemented as described with reference to FIGS. 2 and 3. Thus, reference numerals for elements of FIG. 4 match corresponding elements in the structure of FIGS. 2 and 3. It will be understood that the array structure illustrated in FIG. 4 can be implemented using other cell structures. In a schematic illustration of FIG. 4, the common source line 28, the word line 23 and the word line 24 are arranged generally parallel in the Y-direction. Bit lines 41 and 42 are arranged generally parallel in the X-direction. Thus, a Y-decoder and a word line driver in block 45 are coupled to the word lines 23, 24. An X-decoder and set of sense amplifiers in block 46 are coupled to the bit lines 41 and 42. The common source line 28 is coupled to the source terminals of access transistors 50, 51, 52 and 53. The gate of access transistor 50 is coupled to the word line 23. The gate of access transistor 51 is coupled to the word line 24. The gate of access transistor 52 is coupled to the word line 23. The gate of access transistor 53 is coupled to the word line 24. The drain of access transistor 50 is coupled to the electrode member 32 for bridge 36, which is in turn coupled to electrode member 34. Likewise, the drain of access transistor 51 is coupled to the electrode member 33 for bridge 37, which is in turn coupled to the electrode member 34. The electrode member 34 is coupled to the bit line 41. For schematic purposes, the electrode member 34 is illustrated at separate locations on the bit line 41. It will be appreciated that separate electrode members can be utilized for the separate memory cell bridges in other embodiments. Access transistors 52 and 53 are coupled to corresponding memory cells as well on line 42. It can be seen that the common source line 28 is shared by two rows of memory cells, where a row is arranged in the Y-direction in the illustrated schematic. Likewise, the electrode member 34 is shared by two memory cells in a column in the array, where a column is arranged in the X-direction in the illustrated schematic.

FIG. 5 is a simplified block diagram of an integrated circuit according to an embodiment of the present invention. The integrated circuit 74 includes a memory array 60 implemented using thin film fuse phase change memory cells with thermally insulating blankets, on a semiconductor substrate. A row decoder 61 is coupled to a plurality of word lines 62, and arranged along rows in the memory array 60. A column decoder 63 is coupled to a plurality of bit lines 64 arranged along columns in the memory array 60 for reading and programming data from the thin film phase change memory cells in the array 60. Addresses are supplied on bus 65 to column decoder 63 and row decoder 61. Sense amplifiers and data-in structures in block 66 are coupled to the column decoder 63 via data bus 67. Data is supplied via the data-in line 71 from input/output ports on the integrated circuit 75 or from other data sources internal or external to the integrated circuit 75, to the data-in structures in block 66. In the illustrated embodiment, other circuitry is included on the integrated circuit, such as a general purpose processor or special purpose application circuitry, or a combination of modules providing system-on-a-chip functionality supported by the thin film fuse phase change memory cell array. Data is supplied via the data-out line 72 from the sense amplifiers in block 66 to input/output ports on the integrated circuit 75, or to other data destinations internal or external to the integrated circuit 75.

A controller implemented in this example using bias arrangement state machine 69 controls the application of bias arrangement supply voltages 68, such as read, program, erase, erase verify and program verify voltages. The controller can be implemented using special-purpose logic circuitry as known in the art. In alternative embodiments, the controller comprises a general-purpose processor, which may be implemented on the same integrated circuit, which executes a computer program to control the operations of the device. In yet other embodiments, a combination of special-purpose logic circuitry and a general-purpose processor may be utilized for implementation of the controller.

FIGS. 6-16 illustrate a structure and process based on use of dual-damascene structures for the electrode layer. In a dual-damascene (DD) structure, a dielectric layer is formed in a two level (“dual”) pattern where a first level of the pattern defines trenches for conductor lines and a second level defines vias for connection to underlying structure. A single metal deposition step can be used to simultaneously form conductor lines and deposit material in the vias for connecting the conductor lines to underlying structure. The vias and trenches can be defined by using two lithography steps. Trenches are typically etched to a first depth, and the vias are etched to a second depth making openings for contact to underlying structure. After the vias and trenches are etched, a deposition step fills both the vias and the trenches with metal or other conductive material. After filling, the excess material deposited outside the trench can be removed by a CMP process, and a planar, dual-damascene structure with conductor inlays is achieved.

As shown in FIG. 6, in the dual-damascene process, a layer 651 of an electrically insulating material, usually a dielectric, is formed over the front-end-of-line structures, and acts as a layer in which damascene electrodes are inlaid. Front-end-of-line processing forms the standard CMOS components in the illustrated embodiment corresponding to the word lines, the source line, and the access transistors in the array shown in FIG. 2. In FIG. 6, source line 106 overlies doped region 103 in the semiconductor substrate, where the doped region 103 corresponds with the source terminal of a first access transistor on the left in the figure, and of a second access transistor on the right in the figure. In this embodiment, the source line 106 extends to the top surface of the structure 99. In other embodiments the source line does not extend all the way to the surface. Doped region 104 corresponds with the drain terminal of the first access transistor. A word line including polysilicon 107 acts as the gate of the first access transistor. Dielectric layer (not shown) overlies the polysilicon 107. Plug 110 contacts doped region 104, and provides a conductive path to the surface of the structure 99 for contact to a memory cell electrode as described below. The drain terminal of the second access transistor is provided by doped region 105. A word line including polysilicon line 111 acts as the gate for the second access transistor. Plug 112 contacts doped region 105 and provides a conductive path to the top surface of the structure 99 for contact to a memory cell electrode as described below. Layer 651 overlies these front-end-of-line structures as shown.

The damascene process includes a first patterned photoresist layer 652 which overlies the layer 651, as shown in FIG. 7. The first patterned photoresist layer 652 defines the positions 653, 654, 655 of trenches to be etched in the layer 651, which correspond to the electrode members in the damascene electrode structure.

Using the patterned photoresist layer 652 as a mask, the layer 651 is etched to a first depth so that it is not completely through the layer 651 to form more shallow trenches 656, 657, 658 as shown in FIG. 8. Next, as shown in FIG. 9, a second patterned photoresist layer 659 is formed over the layer 651. The second patterned photoresist layer 659 defines the positions 660, 661 for contact to the plugs 110, 112 by the electrode members. Using the second patterned photoresist layer 659 as a mask, the layer 651 is etched completely through to the plugs 110, 112, to form deeper trenches 662, 663 within the more shallow trenches 656, 657, 658, as shown in FIG. 10.

The resulting dual-trenched layer 651 is filled by a metal, such as copper, or a copper alloy, with appropriate adhesion and barrier layers as known in the art to form the layer 664 illustrated in FIG. 11. As shown in FIG. 12, chemical mechanical polishing or another step is applied to remove the portions of the metal layer 664 down to the dielectric 651, resulting in an electrode layer having a dual-damascene structure, with the electrode structures 665, 666, 667. The electrode structures 665 and 667 have contacts extending down to the plugs 110 and 112, while electrode structure 666 is isolated from the source line 106.

In the next step, shown by FIG. 13, a layer 668 a of memory material, a barrier layer 668 b and a thermally insulating layer 668 c are formed over the damascene dielectric layer 651, referred to as the electrode layer of the device. A patterned photoresist layer, including masks 670 and 671 shown in FIG. 14, is then formed over the layer 668 c. The masks 670 and 671 define the positions of the bridges of memory material for the memory cells. Then, an etch step is applied to remove the layer 669 and the layer of memory material 668 in the regions uncovered by the masks 670 and 671, leaving bridges 672, 673 of multilayer composites including an active layer of memory material, a barrier layer and a thermally insulating layer as described above. The active layer of bridge 672 extends from the electrode structure 665 to the electrode structure 666 across an insulating member 674. The width of the insulating member 674 defines the length of the inter-electrode path through the bridge 672 of memory material. The bridge 673 extends from the electrode structure 667 to the electrode structure 666 across an insulating member 675. The width of the insulating member 675 defines the length of the inter-electrode path through the bridge 673 of memory material.

As illustrated in FIG. 16, after defining the bridges 672, 673, the dielectric fill (not shown) is applied and planarized. Then vias are etched in the dielectric fill over the electrode member 666. The vias are filled with a plug, such as tungsten, to form conductive plug 676. A metal layer is patterned to define bit line 677 which contacts the plug 676, and is arranged along columns of memory cell pairs having a structure illustrated in FIG. 16. The material of the dielectric fill may not be a very good thermally insulating barrier. Thus, the thermally insulating material used in the bridges 672 and 673 has a lower thermal conductivity than that of the material of the overlying dielectric fill.

FIG. 2 illustrates the resulting structure from the dual-damascene electrode layer process, with the dielectric material from the electrode layer 651, shown in FIG. 16 removed for perspective.

Other techniques for implementing a narrow bridge of memory material are shown in our prior U.S. patent application Ser. No. 11/155,067, entitled THIN FILM FUSE PHASE CHANGE RAM AND MANUFACTURING METHOD, filed 17 Jun. 2005, which is incorporated by reference as if fully set forth herein, and such techniques are readily extended to the composite bridge structure described herein to form very narrow layers of active material in the bridges.

Most phase change memory cells known to applicant are made by forming a small pore filled with phase change material, with top and bottom electrodes contacting the phase change material. The small pore structure is used to reduce the programming current. This invention reduces programming current without formation of the small pore, resulting in better process control. Furthermore, there are no top electrodes on the cell, avoiding some possible damage of the phase change material from processes used to form the top electrode.

A cell described herein comprises two bottom electrodes with a dielectric spacer in between and a bridge of phase change material on the top of the electrodes spanning across the spacer. The bottom electrodes and dielectric spacer are formed in an electrode layer over front-end-of-line CMOS logic structures or other function circuit structures, providing a structure that easily supports embedded memory and function circuits on a single chip, such as chips referred to as system-on-a-chip SOC devices.

Advantages of an embodiment described herein include that the phase change happens on the center of the bridge over the dielectric spacer, rather than on the interface with an electrode, providing better reliability. Also, the current used in reset and programming is confined in a small volume allowing high current density and resultant local heating at lower reset current levels and lower reset power levels. The structure in embodiments described herein allows two dimensions of the cell to be defined by thin film thickness, achieving better process control at nanometer scales. Only one dimension of cell can be defined by a lithographic process using a trimmed mask layer, which avoids more complex shrinking techniques.

While the present invention is disclosed by reference to the preferred embodiments and examples detailed above, it is to be understood that these examples are intended in an illustrative rather than in a limiting sense. It is contemplated that modifications and combinations will occur to those skilled in the art, which modifications and combinations will be within the spirit of the invention and the scope of the following claims. What is claimed is: 

1. A memory device, comprising: a first electrode having a top side, a second electrode having a top side; an insulating member between the first electrode and the second electrode, the insulating member having a thickness between the first and second electrodes near the top side of the first electrode and the top side of the second electrode; and a bridge across the insulating member, the bridge having a first side and a second side and contacting the top sides of first and second electrodes on the first side, and defining an inter-electrode path between the first and second electrodes across the insulating member, the inter-electrode path having a path length defined by the width of the insulating member, wherein the bridge comprises an active layer of memory material on the first side having at least two solid phases and a blanket of thermally insulating material overlying the memory material; and a layer of electrically insulating material over the blanket of thermally insulating material, wherein the thermally insulating material of the blanket has a thermal conductivity less than that of the electrically insulating material.
 2. The device of claim 1, wherein the electrically insulating material comprises silicon dioxide.
 3. The device of claim 1, wherein the thickness of the insulating member is about 50 nm or less, and said active layer of memory material comprises a thin film with a thickness about 50 nm or less.
 4. The device of claim 1, wherein the thickness of the insulating member is about 20 nm or less, and said active layer of memory material comprises a thin film with a thickness about 20 nm or less.
 5. The device of claim 1, wherein said active layer of memory material comprises a thin film with a thickness about 10 nm or less.
 6. The device of claim 1, wherein the blanket includes a barrier layer of electrically insulating material between the active layer of memory material and the thermally insulating material of the blanket.
 7. The device of claim 1, wherein the blanket includes a diffusion barrier between the active layer of memory material and the thermally insulating material of the blanket.
 8. The device of claim 1, wherein said thermally insulating material comprises a chalcogenide.
 9. The device of claim 1, wherein said thermally insulating material comprises a polyimide.
 10. The device of claim 1, wherein the at least two solid phases include a generally amorphous phase and a generally crystalline phase.
 11. The device of claim 1, wherein the thickness of the insulating member is less than a minimum lithographic feature size of a lithographic process used to form the device.
 12. The device of claim 1, wherein said active layer of memory material has a thickness between the first and second sides less than a minimum lithographic feature size of a lithographic process used to form the device.
 13. The device of claim 1, wherein the memory material comprises an alloy including a combination of Ge, Sb, and Te.
 14. The device of claim 1, wherein the memory material comprises an alloy including a combination of two or more materials from the group of Ge, Sb, Te, Se, In, Ti, Ca, Bi, Sn, Cu, Pd, Pb, Ag, S, and Au.
 15. A memory device, comprising: a substrate; an electrode layer on the substrate, the electrode layer including an array of electrode pairs having a first electrode having a top surface, a second electrode having a top surface, and an insulating member between the first electrode and the second electrode; an array of bridges across the insulating members of respective electrode pairs, the bridges having respective first sides and second sides and contacting the top surfaces of the first and second electrodes in the respective electrode pairs on the first sides, wherein the bridges respectively comprise an active layer of memory material on the first side having at least two solid phases and a blanket of thermal insulating material overlying the memory material; a layer of electrically insulating material over the array of bridges, wherein the thermally insulating material has thermal conductivity less than that of the electrically insulating material; and bit lines overlying the layer of electrically insulating material, with contacts to bridges in the array of bridges through vias in the layer of electrically insulating material.
 16. The device of claim 15, wherein the thickness of the insulating member is about 50 nm or less, and said active layer of memory material comprises a thin film with a thickness about 50 nm or less.
 17. The device of claim 15, wherein the thickness of the insulating member is about 20 nm or less, and said active layer of memory material comprises a thin film with a thickness about 20 nm or less.
 18. The device of claim 15, wherein said active layer of memory material comprises a thin film with a thickness about 10 nm or less.
 19. The device of claim 15, wherein the blanket includes a barrier layer of insulating material between the active layer of memory material and the thermally insulating material of the blanket.
 20. The device of claim 15, wherein the blanket includes a diffusion barrier between the active layer of memory material and the thermally insulating material of the blanket.
 21. The device of claim 15, wherein said thermally insulating material comprises a chalcogenide.
 22. The device of claim 15, wherein said thermally insulating material comprises a polyimide.
 23. The device of claim 15, wherein the at least two solid phases include a generally amorphous phase and a generally crystalline phase.
 24. The device of claim 15, wherein the thickness of the insulating member is less than a minimum lithographic feature size of a lithographic process used to form the device.
 25. The device of claim 15, wherein said active layer of memory material has a thickness between the first and second sides less than a minimum lithographic feature size of a lithographic process used to form the device.
 26. The device of claim 15, wherein the memory material comprises an alloy including a combination of Ge, Sb, and Te.
 27. The device of claim 15, wherein the memory material comprises an alloy including a combination of two or more materials from the group of Ge, Sb, Te, Se, In, Ti, Ga, Bi, Sn, Cu, Pd, Pb, Ag, S, and Au.
 28. A method for manufacturing a memory device, comprising: forming an electrode layer, the electrode layer including a first electrode and a second electrode, and an insulating member between the first and second electrodes, at a top surface of the electrode layer, the insulating member extending in to form insulating walls on the top surface of the electrode layer, and the insulating member has a width between the first and second electrodes at the top surface; forming a bridge of memory material on the top surface of the electrode layer across the insulating member, the bridge an active layer of memory material in contact with the first and second electrodes, and a thermally insulating blanket over the active layer, the bridge defining an inter-electrode path between the first and second electrodes across the insulating member having a path length defined by the width of the insulating member, wherein the memory material has at least two solid phases; and forming a layer of dielectric material over the bridge, wherein the thermally insulating blanket comprises a thermally insulating material having thermal conductivity less than that of the dielectric material.
 29. The method of claim 28, wherein the width of the insulating member is about 50 nm or less, and said forming a bridge includes forming the patch with a thickness about 50 nm or less.
 30. The method of claim 28, wherein the width of the insulating member is about 20 nm or less, and said forming a bridge includes forming the patch with a thickness about 20 nm or less.
 31. The method of claim 28, wherein said forming a bridge includes forming the patch with a thickness about 10 nm or less.
 32. The method of claim 28, wherein said forming an electrode layer includes defining a plurality of pairs of first and second electrodes, and isolation members separating a pair in the plurality of pairs from another pair in said plurality of pairs.
 33. The method of claim 28, wherein said forming a bridge includes: forming a layer of memory material on the top surface of the electrode layer; forming a layer of thermally insulating material over the layer of memory material; patterning the layer of memory material and the layer of thermally insulating material to define said bridge.
 34. The method of claim 28, wherein said forming the first and second electrodes comprises a dual damascene process. 